1. Field of the Invention
This invention relates generally to circuits and methods for programming memory array structures. More particularly, this invention relates circuits and methods for bi-directionally programming spin moment transfer magnetic random access memory (MRAM) cells in an array.
2. Description of Related Art
The term Spin-RAM refers to a magnetic tunnel junction (MTJ) random access memory (RAM). In this context, the term “spin” refers to the angular momentum of electrons passing through an MTJ that will alter the magnetic moment of a free layer of an MTJ device. Electrons possess both electric charge and angular momentum (or spin). It is known in the art that a current of spin-polarized electrons can change the magnetic orientation of a free ferromagnetic layer of an MTJ via an exchange of spin angular momentum.
“A Novel Nonvolatile Memory with Spin-torque Transfer Magnetization Switching: Spin-Ram”, Hosomi, et al., IEEE International Electron Devices Meeting, 2005. IEDM Technical Digest. December 2005, pp.: 459-462, provides a nonvolatile memory utilizing spin-torque transfer magnetization switching (STS), abbreviated Spin-RAM. The Spin-RAM is programmed by magnetization reversal through an interaction of a spin momentum-torque-transferred current and a magnetic moment of memory layers in magnetic tunnel junctions (MTJs), and therefore an external magnetic field is unnecessary as that for a conventional MRAM.
Refer now to FIG. 1 for an explanation of and spin torque transfer magnetization switching (STS) or spin moment transfer (SMT) in an MTJ element 5 as described Hosomi, et al. A spin-torque MTJ 5 element has two ferromagnetic layers, F1 10 and F2 15, and a spacer layer 20 between the ferromagnetic layers, F1 10 and F2 15. The ferromagnetic layer, F1 10 is a pinned magnetic layer. The spacer layer 20 is a tunnel barrier layer. The ferromagnetic layer F2 15 is a free magnetic layer. When a spin polarized electron 40 flows through the ferromagnetic layers, F1 10 and F2 15, the spin direction 42 rotates according to the directions of magnetic moment M2 55 and M1 50 respectively to the directions 43 and 44. The rotation of spin direction of the electrons in the ferromagnetic layers, F1 10 and F2 15 are the origin of a spin-torque, dM1/dt 47 and dM2/dt 45, to the magnetic moment M1 50 and M2 55. If the given torque is large enough, magnetization of ferromagnetic layer F2 15 and thus the magnetic moment M2 55 is reversed. The magnetization of the ferromagnetic layers, F1 10 and F2 15 transforms from parallel to anti-parallel alignment. This changes the MTJ element 5 from a low resistance state to a high resistance state thus changing the logic state of the MTJ element from a first logic state (0) to a second logic state (1).
The voltage source 35 provides the programming voltage VPROG that generates the programming current iPROG that is reversed appropriately change the programming state of the MTJ element 5.
“2 Mb SPRAM (SPin-Transfer Torque RAM) with Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read”, Kawahara, et al., IEEE Journal of Solid-State Circuits, January 2008, Vol.: 43, Issue: 1, pp: 109-1, Posted online: 2008 Jan. 28 09:50:32.0, describes a 1.8 V, 2 Mb SPRAM chip. The SPRAM chip features an array scheme with bit-by-bit bi-directional current writing to achieve proper spin-transfer torque parallelizing-direction current reading with a low-voltage bit-line for preventing read disturbances.
U.S. Pat. No. 7,272,034 (Chen, et al.) provides a current driven switching of magnetic storage cells utilizing spin transfer in magnetic memories. The magnetic storage cells include a magnetic storage element and one or more selection transistors. The magnetic element is capable of being programmed using spin transfer induced switching by a write current driven through the at least one magnetic element. The selection transistor is configured to allow the magnetic element to be alternately selected for writing and reading.
U.S. Pat. No. 7,286,395 (Chen, et al.) and U.S. Patent Application 2007/0097730 (Chen et al.) teach current driven switched magnetic storage cells having improved read and write margins in a magnetic memory array. The memory array has an array of the magnetic storage cells, at least one bit line, and multiple source lines. Each magnetic storage cell includes a magnetic element that is programmed to a high resistance state by a first write current driven through the magnetic element in a first direction and to a low resistance state by a second write current driven through the magnetic element in a second direction. The bit line(s) and the source lines are configured to drive the first write current through the magnetic element in the first direction, to drive the second write current through the magnetic element in the second direction, and to drive at least one read current through the magnetic element in a third direction that does not destabilize the low resistance state.
U.S. Pat. No. 7,379,327 (Chen, et al.) and U.S. Patent Application 2007/0297223 (Chen, et al.) describe a spin transfer magnetic memory that includes magnetic storage cells in an array, bit lines, and source lines. Each magnetic storage cell includes at least one magnetic element. Each magnetic element has free and pinned layer(s) and a dominant spacer. The magnetic memory is configured such that the direction of the read current(s) flow between the free layer(s) and the dominant spacer by the ratios of the low resistance state read current and the minimum low resistance state write current compared to the ratio of the maximum high resistance state read current minimum high resistance state write current.
U.S. Pat. No. 7,443,718 (Ito, et al.) illustrates writing to a magnetic tunnel junction (MTJ) by providing a current IMTJ through the magnetic tunnel junction. The current IMTJ is at the DC threshold current for a first time duration and then the current IMTJ is driven to a level larger than the DC threshold current for a second time duration to cause the magnetic tunnel junction to switch states.
U.S. Patent Application 2007/0285975 (Kawahara et al.) describes a memory using spin transfer torque. The state of the spin is made unstable by applying a weak pulse before rewriting to reduce rewrite current. Reading of high-speed operation is performed with current in a regime where the current non-linearly increases corresponding to the pulse width to suppress disturb.
U.S. Patent Application 2008/0061388 (Diao et al.) provides magnetic or magnetoresistive tunnel junction devices that have a multilayer insulator barrier layer to produce balanced write switching currents in the device circuitry. Alternately, the devices have balanced critical spin currents required for spin torque transfer induced switching of the magnetization, or both for the MTJs under both the forward and reversed bias directions.